R
XC3000 Series Field Programmable Gate Arrays
XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PGA
Pin
Number
PGA
Pin
Number
PGA
Pin
Number
PGA
Pin
Number
XC3042A
XC3064A
XC3042A
XC3064A
XC3042A
XC3064A
XC3042A
XC3064A
C4
A1
GND
PWRDN
I/O-TCLKIN
I/O
B13
C11
A14
D12
C13
B14
C14
E12
D13
D14
E13
F12
E14
F13
F14
G13
G14
G12
H12
H14
H13
J14
M1-RD
GND
M0-RT
VCC
M2-I/O
HDC-I/O
I/O
P14
M11
N13
M12
P13
N12
P12
N11
M10
P11
N10
P10
M9
N9
RESET
M3
P1
M4
L3
DOUT-I/O
CCLK
VCC
VCC
C3
B2
DONE-PG
D7-I/O
GND
B3
I/O
XTL1-I/O-BCLKIN
M2
N1
M1
K3
L2
A0-WS-I/O
A1-CS2-I/O
I/O
A2
I/O*
I/O
I/O
B4
I/O
C5
A3
I/O
I/O
D6-I/O
I/O
I/O*
I/O
I/O
I/O
A2-I/O
A3-I/O
I/O
A4
LDC-I/O
I/O*
I/O*
L1
B5
I/O
I/O
K2
J3
C6
A5
I/O
I/O
I/O
I/O
I/O
I/O
D5-I/O
K1
J2
A15-I/O
A4-I/O
I/O*
B6
I/O
I/O
CS0-I/O
A6
I/O
I/O
P9
I/O*
J1
B7
I/O
I/O
P8
I/O*
H1
H2
H3
G3
G2
G1
F1
F2
E1
F3
E2
D1
D2
E3
C1
B1
C2
D3
A14-I/O
A5-I/O
GND
C7
C8
A7
GND
VCC
I/O
INIT-I/O
VCC
GND
I/O
N8
D4-I/O
P7
I/O
M8
M7
N7
VCC
VCC
B8
I/O
GND
A13-I/O
A6-I/O
I/O*
A8
I/O
I/O
D3-I/O
A9
I/O
I/O
P6
CS1-I/O
B9
I/O
J13
I/O
N6
I/O*
A12-I/O
A7-I/O
I/O
C9
A10
B10
A11
C10
B11
A12
B12
A13
C12
I/O
K14
J12
I/O
P5
I/O*
I/O
I/O
M6
N5
D2-I/O
I/O
K13
L14
L13
K12
M14
N14
M13
L12
I/O
I/O
I/O
I/O*
I/O
I/O*
P4
I/O
A11-I/O
A8-I/O
I/O
I/O
P3
I/O
I/O
I/O
M5
N4
D1-I/O
I/O*
I/O
I/O
RDY/BUSY-RCLK-I/O
I/O
I/O
P2
I/O
I/O
A10-I/O
A9-I/O
VCC
I/O*
I/O
XTL2(IN)-I/O
GND
N3
N2
D0-DIN-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
* Indicates unconnected package pins (14) for the XC3042A.
7-70
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
