R
XC3000 Series Field Programmable Gate Arrays
XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PGA Pin
Number
PGA Pin
Number
PGA Pin
Number
PGA Pin
Number
XC3090A, XC3195A
XC3090A, XC3195A
XC3090A, XC3195A
XC3090A, XC3195A
B2
D4
PWRDN
TCLKIN-I/O
I/O
D13
B14
C14
B15
D14
C15
E14
B16
D15
C16
D16
F14
E15
E16
F15
F16
G14
G15
G16
H16
H15
H14
J14
I/O
M1-RDATA
GND
M0-RTRIG
VCC
M2-I/O
HDC-I/O
I/O
R14
N13
T14
P13
R13
T13
N12
P12
R12
T12
P11
N11
R11
T11
R10
P10
N10
T10
T9
DONE-PG
N4
R2
P3
N3
P2
M3
R1
N2
P1
N1
L3
DOUT-I/O
CCLK
VCC
D7-I/O
B3
XTL1(OUT)-BCLKIN-I/O
C4
I/O
I/O
GND
A0-WS-I/O
A1-CS2-I/O
I/O
B4
I/O
I/O
A4
I/O
I/O
D5
I/O
I/O
C5
I/O
D6-I/O
I/O
B5
I/O
I/O
I/O
A2-I/O
A3-I/O
I/O
A5
I/O
I/O
I/O
C6
I/O
LDC-I/O
I/O
I/O
D6
I/O
I/O
M2
M1
L2
I/O
B6
I/O
I/O
I/O
A15-I/O
A4-I/O
I/O
A6
I/O
I/O
D5-I/O
B7
I/O
I/O
CS0-I/O
L1
C7
I/O
I/O
I/O
K3
K2
K1
J1
I/O
D7
I/O
I/O
I/O
A14-I/O
A5-I/O
I/O
A7
I/O
I/O
I/O
A8
I/O
I/O
I/O
B8
I/O
I/O
R9
D4-I/O
J2
I/O
C8
I/O
INIT-I/O
VCC
GND
I/O
P9
I/O
J3
GND
VCC
D8
GND
VCC
I/O
N9
VCC
H3
H2
H1
G1
G2
G3
F1
F2
E1
E2
F3
D1
C1
D2
B1
E3
C2
D3
C3
7
D9
N8
GND
A13-I/O
A6-I/O
I/O
C9
J15
P8
D3-I/O
B9
I/O
J16
I/O
R8
CS1-I/O
A9
I/O
K16
K15
K14
L16
L15
M16
M15
L14
N16
P16
N15
R16
M14
P15
N14
R15
P14
I/O
T8
I/O
I/O
A10
D10
C10
B10
A11
B11
D11
C11
A12
B12
C12
D12
A13
B13
C13
A14
I/O
I/O
T7
I/O
I/O
I/O
I/O
N7
I/O
I/O
I/O
I/O
P7
I/O
A12-I/O
A7-I/O
I/O
I/O
I/O
R7
D2-I/O
I/O
I/O
T6
I/O
I/O
I/O
R6
I/O
I/O
I/O
I/O
N6
I/O
A11-I/O
A8-I/O
I/O
I/O
I/O
P6
I/O
I/O
I/O
T5
I/O
I/O
I/O
R5
D1-I/O
I/O
I/O
I/O
P5
RDY/BUSY-RCLK-I/O
A10-I/O
A9-I/O
VCC
I/O
I/O
N5
I/O
I/O
I/O
XTL2(IN)-I/O
GND
RESET
VCC
T4
I/O
R4
I/O
GND
I/O
P4
I/O
I/O
R3
D0-DIN-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist.
November 9, 1998 (Version 3.1)
7-73
XILINX [ XILINX, INC ]
