R
XC3000 Series Field Programmable Gate Arrays
XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PLCC Pin Number
XC3064A, XC3090A, XC3195A
PLCC Pin Number
XC3064A, XC3090A, XC3195A
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
PWRDN
TCLKIN-I/O
I/O
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
RESET
DONE-PG
D7-I/O
I/O
XTL1(OUT)-BCLKIN-I/O
D6-I/O
I/O
I/O
I/O
I/O
D5-I/O
I/O
CS0-I/O
D4-I/O
I/O
GND*
VCC
I/O
I/O
VCC
GND*
I/O
D3-I/O*
CS1-I/O*
D2-I/O*
I/O
I/O
I/O
I/O
I/O
D1-I/O
I/O
RDY/BUSY-RCLK-I/O
D0-DIN-I/O
DOUT-I/O
CCLK
I/O
M1-RDATA
M0-RTRIG
M2-I/O
HDC-I/O
I/O
A0-WS-I/O
A1-CS2-I/O
A2-I/O
LDC-I/O
I/O
A3-I/O
I/O
I/O
I/O
I/O
A15-I/O
A4-I/O
I/O
INIT/I/O*
VCC*
GND
I/O
A14-I/O
A5-I/O
GND
2
VCC*
I/O
3
A13-I/O*
A6-I/O*
A12-I/O*
A7-I/O*
I/O
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
A11-I/O
A8-I/O
I/O
9
I/O
10
11
A10-I/O
A9-I/O
XTL2(IN)-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
* In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin
definition than XC3020A/XC3030A/XC3042A.
7-68
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
