R
XC3000 Series Field Programmable Gate Arrays
XC3100L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
Symbol
-3
-2
Description
Propagation Delays (Input)
Min
Max
Min
Max
Units
Pad to Direct In (I)
Pad to Registered In (Q) with latch (XC3100L)
transparent
3
T
2.2
11.0
2.0
11.0
ns
ns
PID
T
PTG
Clock (IK) to Registered In (Q)
4
1
T
2.2
1.9
ns
IKRI
Set-up Time (Input)
Pad to Clock (IK) set-up time
T
PICK
XC3142L
XC3190L
9.5
9.9
9.0
9.4
ns
ns
Propagation Delays (Output)
Clock (OK) to Pad
same
(fast)
(slew rate limited)
(fast)
7
7
10
10
9
9
8
8
T
T
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
4.0
9.7
3.0
8.7
5.0
5.0
8.5
14.2
ns
ns
ns
ns
ns
ns
ns
ns
OKPO OK
PO
T
T
T
T
T
T
Output (O) to Pad
OPF
OPF
same
(slew-rate limited)(XC3100L)
3-state to Pad begin hi-Z
same
3-state to Pad active and valid(fast)(XC3100L)
(fast)
(slew-rate limited)
TSHZ
TSHZ
TSON
TSON
7
same
(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time (XC3100L)
Output (O) to clock (OK) hold time
5
6
T
T
4.0
0
3.6
0
ns
ns
OOK
OKO
Clock
Clock High time
Clock Low time
Export Control Maximum flip-flop toggle rate
11
12
T
T
1.6
1.6
270
1.3
1.3
325
ns
ns
MHz
IOH
IOL
F
TOG
Global Reset Delays
RESET Pad to Registered In (Q)
(XC3142L)
13
T
16.0
21.0
17.0
23.0
16.0
21.0
17.0
23.0
ns
ns
ns
ns
RRI
(XC3190L)
RESET Pad to output pad
(fast)
15
15
T
T
RPO
RPO
(slew-rate limited)
Advance
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
November 9, 1998 (Version 3.1)
7-63
XILINX [ XILINX, INC ]
