R
XC3000 Series Field Programmable Gate Arrays
XC3100A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
Symbol
-4
-3
-2
-1
-09
Description
Propagation Delays (Input)
Min Max Min Max Min Max Min Max Min Max Units
Pad to Direct In (I)
3
4
TPID
2.5
2.2
2.0
1.7
1.55
ns
Pad to Registered In (Q)
with latch transparent(XC3100A)Clock(IK)
to Registered In (Q)
TPTG
TIKRI
12.0
2.5
11.0
2.2
11.0
1.9
10.0
1.7
9.2
1.55
ns
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3120A, XC3130A
XC3142A
1
TPICK 10.6
10.7
9.4
9.5
9.7
9.9
10.3
8.9
9.0
9.2
9.4
9.8
8.0
8.1
8.3
8.5
8.9
7.2
7.3
7.5
7.7
8.1
ns
ns
ns
ns
ns
XC3164A
XC3190A
XC3195A
11.0
11.2
11.6
Propagation Delays (Output)
Clock (OK) to Pad (fast)
7
7
TOKPO
TOKPO
5.0
12.0
3.7
4.4
10.0
3.3
3.7
9.7
3.0
3.4
8.4
3.0
3.3
6.9
2.9
ns
ns
ns
ns
ns
same
(slew rate limited)
Output (O) to Pad (fast)
10 TOPF
same
(slew-rate limited)
(XC3100A)
10 TOPS
11.0
9.0
8.7
8.0
6.5
3-state to Pad
begin hi-Z
same
(fast)
(slew-rate limited)
9
9
TTSHZ
TTSHZ
6.2
6.2
5.5
5.5
5.0
5.0
4.5
4.5
4.05
4.05
ns
ns
7
3-state to Pad
active and valid (fast) (XC3100A)
same (slew -rate limited)
8
8
TTSON
TTSON
10.0
17.0
9.0
15.0
8.5
14.2
6.5
11.5
5.0
8.6
ns
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
(XC3100A)
5
6
TOOK
TOKO
4.5
0
3.6
0
3.2
0
2.9
ns
ns
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11 TIOH
12 TIOL
FCLK
2.0
2.0
227
1.6
1.6
270
1.3
1.3
323
1.3
1.3
323
1.3
1.3
370
ns
ns
MHz
Global Reset Delays
RESET Pad to Registered In
(Q)
(XC3142A)
(XC3190A)
(fast)
13 TRRI
15.0
25.5
20.0
27.0
13.0
21.0
17.0
23.0
13.0
21.0
17.0
23.0
13.0
21.0
17.0
22.0
14.4
21.0
17.0
21.0
ns
ns
ns
ns
RESET Pad to output pad
15 TRPO
15 TRPO
(slew-rate limited)
Preliminary
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see
XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.
November 9, 1998 (Version 3.1)
7-57
XILINX [ XILINX, INC ]
