R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Figure 41 on page 44 is a diagram of the XC4000 Series
boundary scan logic. It includes three bits of Data Register
per IOB, the IEEE 1149.1 Test Access Port controller, and
the Instruction Register with decodes.
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
XC4000 Series devices can also be configured through the
boundary scan logic. See “Readback” on page 55.
Data Registers
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-State Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PRO-
GRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
two
corresponding
pins
(BSCAN.TDO1
and
BSCAN.TDO2) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to imple-
ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
EXTEST
SLEW
RATE
PULL
DOWN
PULL
UP
M
TS INV
TS/OE
3-State TS
V
CC
6
TS - capture
TS - update
Boundary
Scan
OUTPUT
INVERT
OUTPUT
M
sd
D
Q
Ouput Data O
EC
M
M
INVERT
PAD
M
Ouput Clock OK
rd
OUT
SEL
S/R
M
O - capture
Q - capture
Clock Enable
Boundary
Scan
O - update
M
I - capture
Boundary
Scan
Input Data 1 I1
Input Data 2 I2
I - update
M
M
M
M
sd
Q
D
EC
DELAY
Q
L
M
M
INVERT
M
FLIP-FLOP/LATCH
Input Clock IK
rd
S/R
INPUT
GLOBAL
S/R
X5792
Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).
XC4000X Boundary Scan Logic is Identical.
May 14, 1999 (Version 1.6)
6-43
XILINX [ XILINX, INC ]
