R
XC18V00 Series In-System Programmable Configuration PROMs
VCCO
(See Note 2)
VCCO VCCINT
(See Note 2)
VCCO VCCINT
(See Note 2)
4.7K
MODE PINS
(See Note 1)
MODE PINS
(See Note 1)
DIN
DIN
DOUT
VCCINT
VCCO
D0
VCCINT
VCCO
D0
Xilinx
FPGA
Xilinx
FPGA
XC18V00
XC18V00
VCCO
(See
4.7K
Master
Serial
Slave
Serial
Cascaded
PROM
First
PROM
Note
1)
J1
1
TDI
CLK
CE
TDI
CLK
CE
CCLK
DONE
CCLK
TDI
2
3
4
TMS
TMS
TMS
DONE
TCK
CEO
TCK
CEO
TCK
TDO
OE/RESET
CF
OE/RESET
CF
INIT
INIT
PROGRAM
PROGRAM
TDI
TDI
TDO
TDO
GND
GND
TMS
TCK
TMS
TCK
TDO
TDO
Notes:
1
2
For Mode pin connections and DONE pin pullup value, refer to appropriate FPGA data sheet.
For compatible voltages, refer to the appropriate FPGA data sheet.
DS026_08_061003
Figure 5: Configuring Multiple Devices in Master/Slave Serial Mode
(2)
VCCO
(2)
VCCINT
(2)
VCCINT
VCCO
VCCO
4.7K
(1)
MODE PINS
MODE PINS
**D[0:7]
(3)
D[0:7]
(3)
(3)
D[0:7]
VCCINT
VCCO
D[0:7]
VCCINT
VCCO
Xilinx
Virtex-II
FPGA
Xilinx
Virtex-II
FPGA
(2)
VCCO
XC18V00
XC18V00
4.7K
Master
Serial/
SelectMAP
Slave
Serial/
SelectMAP
Cascaded
PROM
First
PROM
(1)
J1
1
TDI
CLK
CE
TDI
CLK
CCLK
CCLK
TDI
2
3
4
TMS
TMS
TMS
CE
DONE
DONE
TCK
CEO
TCK
CEO
TCK
TDO
OE/RESET
CF
OE/RESET
CF
INIT
INIT
PROGRAM
PROGRAM
TDI
TDI
TDO
TDO
GND
GND
TMS
TCK
TMS
TCK
TDO
TDO
Notes:
1
2
3
For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
For compatible voltges, refer to the appropriate FPGA data sheet.
Master/Slave Serial Mode does not require D[1:7] to be connected.
DS026_09_051003
Figure 6: Configuring Multiple Virtex-II Devices with Identical Patterns in Master/Slave or Serial/SelectMAP Modes
10
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DS026 (v4.0) June 11, 2003
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
