XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
* If Readback is
Activated, a
3.3-kΩ Resistor is
Required in
Series With M1
During Configuration
the 3.3 kΩ M2 Pull-Down
Resistor Overcomes the
Internal Pull-Up,
but it Allows M2 to
be User I/O.
*
Vcc
M0 M1 PWRDWN
DOUT
M2
HDC
General-
Purpose
User I/O
Pins
LDC
INIT
•
•
•
•
•
OPTIONAL
Daisy-chained
FPGAs with
Different
Configurations
Other
I/O Pins
OPTIONAL
Slave FPGAs
with Identical
Configurations
Vcc
FPGA
RESET
RESET
DIN
CCLK
D/P
INIT
VCC
DATA
CLK
CE
OE/RESET
VPP
DATA
CLK Cascaded
Serial
CE
Memory
OE/RESET
SCP
CEO
(Low Resets the Address Pointer)
CCLK
(OUTPUT)
DIN
DOUT
(OUTPUT)
X8256
Figure 2: Master Serial Mode.
The one-time-programmable Serial Configuration PROM supports automatic loading of
configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the
PROM data output one CCLK cycle before the FPGA I/Os become active.
5-4
December 10, 1997 (Version 1.1)
XILINX [ XILINX, INC ]
