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X9241AYV 参数 Datasheet PDF下载

X9241AYV图片预览
型号: X9241AYV
PDF下载: 下载PDF文件 查看货源
内容描述: 四数控电位器( XDCP ) [Quad Digitally Controlled Potentiometer (XDCP)]
分类和应用: 转换器电位器数字电位计电阻器光电二极管
文件页数/大小: 18 页 / 365 K
品牌: XICOR [ XICOR INC. ]
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X9241A  
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)  
Limits  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Test Condition  
l
Supply current (active)  
3
mA  
f
= 100kHz, SDA = Open,  
SCL  
CC  
Other Inputs = V  
SS  
I
V
current (standby)  
200  
500  
10  
µA  
µA  
µA  
V
SCL = SDA = V , Addr. = V  
CC SS  
SB  
CC  
I
Input leakage current  
Output leakage current  
Input HIGH voltage  
Input LOW voltage  
Output LOW voltage  
V
V
= V to V  
SS CC  
LI  
IN  
I
10  
= V to V  
OUT SS CC  
LO  
V
2
V
+ 1  
CC  
IH  
V
–1  
0.8  
0.4  
V
IL  
V
V
I
= 3mA  
OL  
OL  
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used  
as a potentiometer.  
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten-  
tiometer. It is a measure of the error in step size.  
(3) MI = RTOT/63 or (R –R )/63, single pot  
H
L
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.  
ENDURANCE AND DATA RETENTION  
Parameter  
Minimum endurance  
Data retention  
Min.  
100,000  
100  
Unit  
Data changes per bit per register  
Years  
CAPACITANCE  
Symbol  
Parameter  
Max.  
Unit  
pF  
Test Condition  
(5)  
C
Input/output capacitance (SDA)  
19  
12  
V
= 0V  
= 0V  
I/O  
I/O  
(5)  
C
Input capacitance (A0, A1, A2, A3 and SCL)  
pF  
V
IN  
IN  
POWER-UP TIMING  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
1
Unit  
ms  
(6)  
t
Power-up to initiation of read operation  
Power-up to initiation of write operation  
PUR  
(6)  
t
5
ms  
PUW  
t V  
V
Power up ramp rate  
0.2  
50  
V/msec  
R CC  
CC  
POWER-UP REQUIREMENTS (Power Up sequencing can affect correct recall of the wiper registers)  
The preferred power-on sequence is as follows: First Vcc, then the potentiometer pins. It is suggested that Vcc  
reach 90ꢀ of its final value before power is applied to the potentiometer pins. The Vcc ramp rate specification  
should be met, and any glitches or slope changes in the Vcc line should be held to <100mV if possible. Also, Vcc  
should not reverse polarity by more than 0.5V.  
Notes: (5) This parameter is guaranteed by characterization or sample testing.  
(6) t  
and t  
are the delays required from the time V  
is stable until the specified operation can be initiated. These parameters  
PUR  
PUW  
CC  
are guaranteed by design.  
(7) This parameter is guaranteed by design.  
(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.  
(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse  
width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure  
to the device.  
Characteristics subject to change without notice. 11 of 18  
REV 1.1.13 12/09/02  
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