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X9221YST2 参数 Datasheet PDF下载

X9221YST2图片预览
型号: X9221YST2
PDF下载: 下载PDF文件 查看货源
内容描述: [Digital Potentiometer, 2 Func, 2000ohm, 2-wire Serial Control Interface, 64 Positions, CMOS, PDSO20, PLASTIC, SOIC-20]
分类和应用: 光电二极管转换器电阻器
文件页数/大小: 15 页 / 345 K
品牌: XICOR [ XICOR INC. ]
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X9221
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and dur-
ing this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data. See Figure 7.
The X9221 will respond with an acknowledge after rec-
ognition of a start condition and its slave address and
once again after successful receipt of the command
byte. If the command is followed by a data byte the
X9221 will respond with a final acknowledge.
Array Description
The X9221 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V
W
/
R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9221 compares the
serial data stream with the address input state; a suc-
cessful compare of all four address bits is required for
the X9221 to respond with an acknowledge.
Acknowledge Polling
The disabling of the inputs, during the internal nonvola-
tile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9221 initiates the internal
write cycle. ACK polling can be initiated immediately.
This involves issuing the start condition followed by the
device slave address. If the X9221 is still busy with the
write operation no ACK will be returned. If the X9221
has completed the write operation an ACK will be
returned and the master can then proceed with the
next operation.
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter ACK Polling
en
d
ed
fo
r
ec
om
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9221 this is
fixed as 0101[B].
m
N
Issue Slave
Address
ew
Issue
START
YES
YES
D
es
NO
NO
ACK
Returned?
ot
R
Further
Operation?
Figure 1. Slave Address
Device Type
Identifier
0
1
0
1
A3
A2
A1
A0
N
Issue
Instruction
Proceed
Device Address
ig
ns
Issue STOP
Issue STOP
Proceed
REV 1.1 8/8/02
www.xicor.com
Characteristics subject to change without notice.
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