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X24325P 参数 Datasheet PDF下载

X24325P图片预览
型号: X24325P
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的2线串行é 2 PROM带座锁TM保护 [Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection]
分类和应用: 可编程只读存储器
文件页数/大小: 17 页 / 81 K
品牌: XICOR [ XICOR INC. ]
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X24325  
DEVICE ADDRESSING  
The last bit of the slave address defines the operation to  
be performed. When set HIGH a read operation is  
selected, when set LOW a write operation is selected.  
Following a start condition the master must output the  
address of the slave it is accessing (see Figure 4). The  
next three bits are the device select bits. A system  
could have up to eight X24325’s on the bus. The eight  
Following the start condition, the X24325 monitors the  
SDA bus comparing the slave address being transmitted  
with its slave address device type identifier. Upon a  
correct compare the X24325 outputs an acknowledge on  
the SDA line. Depending on the state of the R/W bit, the  
X24325 will execute a read or write operation.  
addresses are defined by the state of the S , S1 and  
0
S2 inputs. S and S2 of the slave address must be the  
0
inverse of the S and S2 input pins.  
0
Figure 4. Slave Address  
WRITE OPERATIONS  
Byte Write  
HIGH ORDER  
DEVICE  
SELECT  
WORD  
ADDRESS  
For a write operation, the X24325 requires a second ad-  
dress field. This address field is the word address, com-  
prised of eight bits, providing access to any one of 4096  
words in the array. Upon receipt of the word address, the  
X24325 responds with an acknowledge and awaits the  
next eight bits of data, again responding with an acknowl-  
edge. The master then terminates the transfer by gener-  
ating a stop condition, at which time the X24325 begins  
the internal write cycle to the nonvolatile memory. While  
the internal write cycle is in progress the X24325 inputs  
are disabled, and the device will not respond to any re-  
quests from the master. Refer to Figure 5 for the address,  
acknowledge and data transfer sequence.  
A10  
A11  
S
S
1
S
A9  
A8 R/W  
2
0
6552 ILL F07.2  
The next four bits of the slave address are an exten-  
sion of the array’s address and are concatenated with  
the eight bits of address in the word address field,  
providing direct access to the whole 4096 x 8 array.  
Figure 5. Byte Write  
S
T
S
SLAVE  
ADDRESS  
WORD  
ADDRESS  
A
R
T
T
BUS ACTIVITY:  
MASTER  
DATA  
O
P
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24325  
6552 ILL F08  
5
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