X24026
Sequential Read
The data output is sequential, with the data from address
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during one
operation. At the end of the address space (address
255), the counter “rolls over” to address 0 and the
X24026 continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowledge
and data transfer sequence.
Sequential Read can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the master
now responds with an acknowledge, indicating it requires
additional data. The X24026 continues to output data for
each acknowledge received. The master terminates this
transmission by issuing a stop condition, omitting the
ninth clock cycle acknowledge.
Figure 9. Sequential Read
S
SLAVE
ADDRESS
T
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
O
P
P
SDA LINE
A
C
K
BUS ACTIVITY:
X24026
DATA n
DATA n+1
DATA n+2
DATA n+x
7020 FRM 12
8
XICOR [ XICOR INC. ]
