X24026
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave are the device type identifier (see
Figure 4). For the X24026 this is fixed as 1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
Following the start condition, the X24026 monitors the
SDA bus comparing the slave address being transmitted
with its slave address. Upon a correct compare the
X24026 outputs an acknowledge on the SDA line.
Depending on the state of the R/W bit, the X24026 will
execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24026 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 256 words of memory. Upon receipt of the word
address the X24026 responds with an acknowledge, and
awaits the next eight bits of data, again responding with
an acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24026
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24026
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
1
0
1
0
0
0
0
R/W
RESERVE
ADDRESS
BITS
7020 FRM 06
The next three significant bits are reserved address bits.
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operations is selected.
Figure 5. Byte Write
S
T
BUS ACTIVITY:
A
R
MASTER
T
SDA LINE
BUS ACTIVITY:
X24026
S
A
C
K
SLAVE
ADDRESS
WORD
ADDRESS
DATA
S
T
O
P
P
A
C
K
A
C
K
7020 FRM 07
Figure 6. Page Write
S
T
BUS ACTIVITY:
A
R
MASTER
T
SDA LINE
BUS ACTIVITY:
X24026
S
SLAVE
ADDRESS
WORD
ADDRESS (n)
DATA n
DATA n+1
DATA n+3
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
7020 FRM 08
5
XICOR [ XICOR INC. ]
