X20C17
PIN CONFIGURATION
Plastic
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
X20C17
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
A
9
WE
OE
A
10
CE
I/O
5
I/O
4
I/O
3
I/O2
I/O
1
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read and recall operations.
Output Enable LOW disables a store operation regard-
less of the state of
CE
,
WE
.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X20C17 through the
I/O pins. The I/O pins are placed in the high impedance
state when either
CE
or OE is HIGH.
Write Enable (
WE
)
The Write Enable input controls the writing of data to
the static RAM.
PIN NAMES
Symbol
A
0
–A
10
SOIC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
I/O
0
–I/O
7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
V
SS
I/O
2
I/O1
I/O
0
A
0
A
1
A
2
NC
OE
WE
A
9
NC
A
8
V
CC
NC
A
7
A
6
A
5
NC
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X20C17
WE
CE
OE
V
CC
V
SS
DEVICE OPERATION
The
CE
, OE, and
WE
inputs control the X20C17 opera-
tion. The X20C17 byte-wide NOVRAM uses a 2-line
control architecture to eliminate bus contention in a
system environment. The I/O bus will be in a high
impedance state when either OE or
CE
is HIGH.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation
requires
CE
and OE to be LOW. A write operation
requires
CE
and
WE
to be LOW. There is no limit to the
number of read or write operations performed to the
RAM portion of the X20C17.
Memory Transfer Operations
There are two memory transfer operations: a recall
operation whereby the data stored in the E
2
PROM
array is transferred to the RAM array; and a store oper-
ation which causes the entire contents of the RAM
array to be stored in the E
2
PROM array.
PIN DESCRIPTIONS
Addresses (A
0
–A
10
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (
CE
)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consump-
tion is reduced.
Characteristics subject to change without notice.
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XICOR [ XICOR INC. ]
