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X1242V8I 参数 Datasheet PDF下载

X1242V8I图片预览
型号: X1242V8I
PDF下载: 下载PDF文件 查看货源
内容描述: [Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, TSSOP-8]
分类和应用: 时钟光电二极管外围集成电路
文件页数/大小: 24 页 / 145 K
品牌: XICOR [ XICOR INC. ]
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Preliminary Information
16k (2k x 8)
X1242
DESCRIPTION
2-Wire
RTC
Real Time Clock/Calendar/Alarms/CPU Supervisor with EEPROM
FEATURES
Selectable watchdog timer (0.25s, 0.75s, 1.75s, off)
Power on reset (250ms)
Programmable low voltage reset
2 polled alarms
—Settable on the second, minutes, hour, day,
month, or day of the week
2-wire interface interoperable with I
2
C
—400kHz data transfer rate
Secondary power supply input with internal
switch-over circuitry
2Kbytes of EEPROM
—64-byte page write mode
—3-bit Block Lock
protection
Low power CMOS
—<1µA operating current
—<3mA active current–EEPROM program
—<400µA active current–EEPROM read
Single byte write capability
Typical nonvolatile write cycle time: 5ms
High reliability
Small package options
—8-lead SOIC package, 8-lead TSSOP package
The X1242 is a Real Time Clock with calendar/CPU
supervisor circuits and two polled alarms. The dual port
clock and alarm registers allow the clock to operate,
without loss of accuracy, even during read and write
operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction and
automatic adjustment for months with less than 31
days.
The X1242 provides a watchdog timer with 3 selectable
time out periods and off. The watchdog activates a
RESET pin when it expires. The reset also goes active
when V
CC
drops below a fixed trip point. There are two
alarms where a match is monitored by polling status bits.
The device offers a backup power input pin. This V
BACK
pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational from
1.8 to 5.5 volts.
The X1242 provides a 2Kbyte EEPROM array, giving a
safe, secure memory for critical user and configuration
data. This memory is unaffected by complete failure of
the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
Oscillator
X2
Frequency
Divider
1Hz
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
8
RESET
Watchdog
Timer
Low Voltage
Reset
Mask
Serial
Interface
Decoder
Control
Decode
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Compare
Alarm Regs
(EEPROM)
16k (2k x 8)
EEPROM
Array
REV 1.1.7 5/31/01
www.xicor.com
Characteristics subject to change without notice.
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