X1242 – Preliminary Information
Figure 3. Block Protect Bits
BP2
BP1
BP0
Protected Addresses
X1242
None
600
h
- 7FF
h
400
h
- 7FF
h
000
h
- 7FF
h
000
h
- 03F
h
000
h
- 07F
h
000
h
- 0FF
h
000
h
- 1FF
h
Array Lock
None
Upper 1/4
Upper 1/2
Full Array
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First 2 pgs
First 4 pgs
First 8 pgs
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode. See
Figure 13. Use the following sequence.
start AE ack 3F ack 02 ack stop
Followed by
start AE ack 3F ack 06 ack stop
– The RWEL and WEL bits can be reset by writing a 0
to the Status Register.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
POWER ON RESET
Application of power to the X1242 activates a Power
On Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power
up.
When V
CC
exceeds the device V
TRIP
threshold value
for 250ms the circuit releases RESET, allowing the
system to begin operation.
WATCHDOG TIMER OPERATION
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 dif-
ferent time out periods or off. When the Watchdog
timer is set to off, the watchdog circuit is configured for
low power operation.
Watchdog Timer Restart
The Watchdog Timer is restarted by a falling edge of
SDA when the SCL line is high. This is also referred to
as start condition. The restart signal restarts the
watchdog timer counter, resetting the period of the
counter back to the maximum. If another start fails to
be detected prior to the watchdog timer expiration,
then the reset pin becomes active. In the event that the
restart signal occurs during a reset time out period, the
restart will have no effect.
Characteristics subject to change without notice.
Watchdog Timer Control Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Figure 4. Watchdog Timer Time Out Options
WD1 WD0
0
0
1
1
0
1
0
1
Watchdog Time Out Period
1.75 seconds
750 milliseconds
250 milliseconds
disabled
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/con-
trol register requires the following steps:
– Write a 02H to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
– Write a 06H to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write write
cycle, so the sequence must be repeated to again
initiate another change to the CCR contents. If the
REV 1.1.7 5/31/01
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