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X1240 参数 Datasheet PDF下载

X1240图片预览
型号: X1240
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟/日历与EEPROM [Real Time Clock/Calendar with EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 19 页 / 78 K
品牌: XICOR [ XICOR INC. ]
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X1240  
DEVICE ADDRESSING  
Following the Slave Byte is a two byte word address.  
The word address is either supplied by the master  
device or obtained from an internal counter. On power  
up the internal address counter is set to address 0h,  
so a current address read of the EEPROM array starts  
at address 0. When required, as part of a random  
read, the master device must supply the 2 Word  
Address Bytes.  
Following a start condition, the master must output a  
Slave Address Byte. The first four bits of the Slave  
Address Byte specify access to the EEPROM array or  
to the CCR. Slave bits ‘1010’ access the EEPROM  
array. Slave bits ‘1101’ access the CCR.  
Bit 3 through Bit 1 of the slave byte specify the device  
select bits. These are set to ‘111’.  
In a random read operation, the slave byte in the  
“dummy write” portion must match the slave byte in  
the “read” section. That is if the random read is from  
the array the slave byte must be ‘1010111x’ in both  
instances. Similarly, for a random read of the Clock/  
Control Registers, the slave byte must be ‘1101111x’  
in both places.  
The last bit of the Slave Address Byte defines the  
operation to be performed. When this R/W bit is a one,  
then a read operation is selected. A zero selects a  
write operation. Refer to Figure 12.  
After loading the entire Slave Address Byte from the  
SDA bus, the device compares the device identifier  
and device select bits with ‘1010111’ or ‘1101111’.  
Upon a correct compare, the device outputs an  
acknowledge on the SDA line.  
Figure 12. Sequential Read Sequence  
S
Slave  
Address  
A
C
K
A
C
K
A
C
K
Signals from  
the Master  
t
o
p
SDA Bus  
1
A
C
K
Signals from  
the Slave  
Data  
(2)  
Data  
(n-1)  
Data  
(1)  
Data  
(n)  
(n is any integer greater than 1)  
11