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X1202V8-4.5A 参数 Datasheet PDF下载

X1202V8-4.5A图片预览
型号: X1202V8-4.5A
PDF下载: 下载PDF文件 查看货源
内容描述: [Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, TSSOP-8]
分类和应用: 时钟光电二极管外围集成电路
文件页数/大小: 23 页 / 173 K
品牌: XICOR [ XICOR INC. ]
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X1202  
Figure 13. Acknowledge Polling Sequence  
READ OPERATIONS  
There are three basic read operations: Current  
Address Read, Random Read, and Sequential Read.  
Byte Load Completed  
by Issuing STOP.  
Enter ACK Polling  
Current Address Read  
Internally the device contains an address counter that  
maintains the address of the last word read incrimi-  
nated by one. Therefore, if the last read was to address  
n, the next read operation would access data from  
address n + 1.  
Issue START  
Issue Slave  
Issue STOP  
Address Byte  
(Read or Write)  
Upon receipt of the slave address byte with the R/W bit  
set to one, the device issues an acknowledge and then  
transmits the eight bits of the data byte. The master  
terminates the read operation when it does not  
respond with an acknowledge during the ninth clock  
and then issues a stop condition. Refer to Figure 14 for  
the address, acknowledge, and data transfer sequence.  
NO  
NO  
ACK  
Returned?  
YES  
Nonvolatile Write  
Cycle Complete.  
Continue Command  
Sequence?  
It should be noted that the ninth clock cycle of the read  
operation is not a “don’t care.” To terminate a read  
operation, the master must either issue a stop condi-  
tion during the ninth cycle or hold SDA HIGH during  
the ninth clock cycle and then issue a stop condition.  
Issue STOP  
YES  
Continue Normal  
Read or Write  
Command  
Sequence  
PROCEED  
Figure 14. Current Address Read Sequence  
S
S
t
o
p
t
a
r
Signals from  
the Master  
Slave  
Address  
t
SDA Bus  
1 1 0 1 1 1 1 1  
A
C
K
Signals from  
the Slave  
Data  
Characteristics subject to change without notice. 12 of 23  
REV 1.1.8 5/17/01  
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