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X1202V8 参数 Datasheet PDF下载

X1202V8图片预览
型号: X1202V8
PDF下载: 下载PDF文件 查看货源
内容描述: [Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, TSSOP-8]
分类和应用: 时钟光电二极管外围集成电路
文件页数/大小: 23 页 / 173 K
品牌: XICOR [ XICOR INC. ]
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X1202  
Write Cycle Timing  
SCL  
SDA  
8th Bit of Last Byte  
ACK  
t
WC  
Stop  
Start  
Condition  
Condition  
Power Up Timing  
Symbol  
Parameter  
Min.  
Typ.(2)  
Max.  
Unit  
ms  
(1)  
t
Time from power up to read  
Time from power up to write  
1
5
PUR  
(1)  
t
ms  
PUW  
Notes: (1) Delays are measured from the time V  
is stable until the specified operation can be initiated. These parameters are periodically  
CC  
sampled and not 100% tested.  
(2) Typical values are for T = 25°C and V = 5.0V  
A
CC  
Nonvolatile Write Cycle Timing  
Symbol  
Parameter  
Min.  
Typ.(1)  
Max.  
Unit  
(1)  
t
Write cycle time  
5
10  
ms  
WC  
Note: (1) t  
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.  
WC  
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.  
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
V
Pre-programmed reset trip voltage  
PTRIP  
X1202-4.5A  
X1202  
X1202-2.7A  
X1202-2.7  
4.49  
4.25  
2.76  
2.57  
4.63  
4.38  
2.85  
2.65  
4.77  
4.51  
2.94  
2.73  
V
t
V
detect to RESET LOW  
500  
400  
ns  
ms  
µs  
µs  
RPD  
CC  
t
Power up reset time out delay  
100  
10  
200  
PURST1  
t
V
V
fall time  
rise time  
F
CC  
t
10  
R
CC  
t
Watchdog timer period:  
WD1 = 0, WD0 = 0  
WD1 = 0, WD0 = 1  
WD1 = 1, WD0 = 0  
WDO  
1.7  
725  
225  
1.75  
750  
250  
1.8  
775  
275  
s
ms  
ms  
t
t
Watchdog reset time out delay  
2-wire interface  
225  
1
250  
275  
ms  
µs  
V
RST1  
RSP  
V
Reset valid V  
1.0  
RVALID  
CC  
Characteristics subject to change without notice. 18 of 23  
REV 1.1.8 5/17/01  
www.xicor.com  
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