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X1202V8 参数 Datasheet PDF下载

X1202V8图片预览
型号: X1202V8
PDF下载: 下载PDF文件 查看货源
内容描述: [Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, TSSOP-8]
分类和应用: 时钟光电二极管外围集成电路
文件页数/大小: 23 页 / 173 K
品牌: XICOR [ XICOR INC. ]
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X1202  
Figure 11. Byte Write Sequence  
S
S
t
o
p
t
Slave  
Address  
Signals from  
the Master  
CCR  
Address 1  
CCR  
Address 0  
a
Data  
r
t
SDA Bus  
0 0 0 0 0 0 0 0  
1 1 0 1 1 1 1 0  
A
C
K
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
Figure 12. Page Write Sequence  
(1 n 64)  
S
t
a
r
Signals from  
the Master  
S
t
o
p
CCR  
Address 1  
Slave  
Address  
CCR  
Address 0  
Data  
(n)  
Data  
(1)  
t
SDA Bus  
1 1 0 1 1 1 1 0  
0 0 0 0 0 0 0 0  
A
C
K
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
After the receipt of each byte, the X1202 responds with  
an acknowledge, and the address is internally incrimi-  
nated by one. When the counter reaches the end of the  
page, it “rolls over” and goes back to the first address  
on the same page. If the master supplies more than 8  
bytes of data, then the previously loaded data is over  
written by the new data, one byte at a time. The master  
terminates the data byte loading by issuing a stop con-  
dition, which causes the device to begin the non vola-  
tile write cycle. As with the byte write operation, all  
inputs are disabled until completion of the internal write  
cycle. Refer to Figure 12 for the address, acknowledge,  
and data transfer sequence.  
Acknowledge Polling  
The disabling of the inputs during non volatile write  
cycles can be used to take advantage of the typical  
5ms write cycle time. Once the stop condition is issued  
to indicate the end of the master’s byte load operation,  
the device initiates the internal non volatile write cycle.  
Acknowledge polling can be initiated immediately. To  
do this, the master issues a start condition followed by  
the slave address byte for a write or read operation. If  
the device is still busy with the non volatile write cycle  
then no ACK will be returned. If the device has com-  
pleted the write operation, an ACK will be returned and  
the host can then proceed with the read or write opera-  
tion. Refer to the flow chart in Figure 13.  
Stops and Write Modes  
Stop conditions that terminate write operations must  
be sent by the master after sending at least 1 full data  
byte and its associated ACK signal. If a stop is issued  
in the middle of a data byte, or before 1 full data byte +  
ACK is sent, then the device will reset itself without  
performing the write. The contents of the array will not  
be affected.  
Characteristics subject to change without notice. 11 of 23  
REV 1.1.8 5/17/01  
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