(3) Read the pattern after bake and perform endpoint electrical tests for table II herein for group C.
4.3.3 Groups D inspections. Group D inspection shall be in accordance with table IV of method 5005 of MIL-STD-883 and as
follows:
a. End-point electrical parameters shall be as specified in table II herein.
b. All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit
pattern.
TABLE II. Electrical test requirements. 1/ 2/ 3/ 4/ 5/
MIL-STD-883 test requirements
Subgroups
(in accordance with
MIL-STD-883, method 5005,
table I)
Interim electrical parameters
(method 5004)
1, 7, 9 or 2, 8A, 10
1*, 2, 3, 7*, 8, 9, 10, 11
1, 2, 3, 4**, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10 ,11
Final electrical test parameters
(method 5004)
Group A test requirements
(method 5005)
Groups C and D end-point
electrical parameters
(method 5005)
1/ (*) Indicates PDA applies to subgroups 1 and 7.
2/ Any or all subgroups may be combined when using multifunction testers.
3/ Subgroup 7 and 8 shall consist of writing and reading the data pattern specified
in accordance with the limits of table I subgroups 9, 10, and 11.
4/ For all electrical tests, the device shall be programmed to the data pattern specified.
5/ (**) Indicates that subgroup 4 will only be performed during initial qualification and after
design or process changes (see 4.3.1c).
4.4 Methods of inspection. Methods of inspection shall be as specified in the appropriate tables of method 5005 of
MIL-STD-883 and as follows.
4.4.1 Voltage and current. All voltages given are referenced to the microcircuit VSS terminal. Currents given are conventional
current and positive when flowing into the referenced terminal.
4.4.2 Programming procedure. The following procedure shall be followed when programming (Write) is performed. The
waveforms and timing relationships shown on figure 5 (in accordance with appropriate device type) and the conditions specified
in table I shall be adhered to. Information is introduced by selectively programming a TTL low or TTL high on each I/O of the
address desired. Functionality shall be verified at all temperatures (group A subgroups 7 and 8) by programming all bytes of
each device and verifying the pattern used.
4.4.3 Erasing procedure. There are two forms of erasure, chip and byte, whereby all bits or the address selected will be
erased to a TTL high.
a. Chip erase is performed in accordance with the waveforms and timing relationships shown on figure 8 (in accordance
with appropriate device type) and the conditions specified in table I.
SIZE
STANDARD
5962-88525
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
22
DSCC FORM 2234
APR 97
XICOR [ XICOR INC. ]
