WM9707
Advanced Information
WARM RESET
tSYNC_HIGH
tSYNC2CLK
SYNC
BIT_CLK
Figure 3 Warm Reset Timing
PARAMETER
SYMBOL
tSYNC_HIGH
MIN
TYP
MAX
UNIT
µs
SYNC active high pulse width
1.3
SYNC inactive to BIT_CLK startup tSYNC2_CLK
delay
162.4
ns
CLOCK SPECIFICATIONS
tCLK_HIGH
tCLK_LOW
BIT_CLK
tCLK_PERIOD
tSYNC_HIGH
tSYNC_LOW
SYNC
tSYNC_PERIOD
Figure 4 Clock Specifications (50pF External Load)
Note: Worst case duty cycle restricted to 40/60.
PARAMETER
SYMBOL
tCLK_PERIOD
tCLK_HIGH
MIN
TYP
MAX
UNIT
MHz
ns
BIT_CLK frequency
BIT_CLK period
12.288
81.4
BIT_CLK output jitter
BIT_CLK high pulse width
( See Note)
750
ps
32.56
32.56
40.7
40.7
48.84
ns
BIT_CLK low pulse width
( See Note)
tCLK_LOW
48.84
ns
SYNC frequency
SYNC period
48.0
20.8
1.3
kHz
µs
tSYNC_PERIOD
tSYNC_HIGH
tSYNC_LOW
SYNC high pulse width
SYNC low pulse width
µs
19.5
µs
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
