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WM9707 参数 Datasheet PDF下载

WM9707图片预览
型号: WM9707
PDF下载: 下载PDF文件 查看货源
内容描述: AC97 2.1版音频编解码器SPDIF输出 [AC97 Revision 2.1 Audio Codec with Spdif Output]
分类和应用: 解码器编解码器光电二极管
文件页数/大小: 30 页 / 237 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM9707  
Advanced Information  
There is no provision for pseudo-stereo effects. Mono signals will have no enhancement applied  
(if the signals are in phase and of the same amplitude).  
Signals from the PCM DAC channels can have stereo enhancement applied. It can also be bypassed  
if desired. This control is enabled by setting the POP bit in Register 20h.  
VARIABLE SAMPLE RATE SUPPORT  
The DACs and ADCs on this device support all the recommended sample rates specified in the Intel  
Revision 2.1 specification for audio rates. The default rate is 48ks/s. If alternative rates are selected  
and variable rate audio is enabled (Register 2Ah, bit 0), the AC97 interface continues to run at 48k  
words per second, but data is transferred across the link in bursts such that the net sample rate  
selected is achieved. It is up to the AC97 Revision 2.1 compliant controller to ensure that data is  
supplied to the AC link, and received from the AC link, at the appropriate rate.  
The device supports on demand sampling. That is, when the DAC signal processing circuits need  
another sample, a sample request is sent to the controller which must respond with a data sample in  
the next frame it sends. For example, if a rate of 24ks/s is selected, on average the device will  
request a sample from the controller every other frame, for each of the stereo DACs. Note that if an  
unsupported rate is written to one of the rate registers, the rate will default to the nearest rate  
supported. The Register will then respond when interrogated with the supported rate the device has  
defaulted to.  
The left and right channels of the ADCs and DACs always sample at the same rate.  
AUDIO  
SAMPLE RATE  
CONTROL VALUE  
D15-D0  
1F40  
8000  
11025  
16000  
22050  
44100  
48000  
2B11  
3E80  
5622  
AC44  
BB80  
Table 1 Variable Sample Rates Supported  
SPDIF DIGITAL AUDIO DATA OUTPUT  
Pin 48 may be used to output the PCM DAC playback data in SPDIF (IEC958) digital data format. In  
order to enable this output, bit SPDF in Register 5Ch should be set or pin 44 pulled high.  
Additionally, a bit SCMS in Register 5Ch may also be set, which removes the copyright flag in the  
IEC958 data, allowing serial copy protect mechanisms to be implemented. Note that this data output  
will only operate at the SYNCH rate and so only supports 48ks/s operation. The PCM DACs continue  
to function normally when SPDIF output is enabled.  
GAIN CONTROL REGISTER LOCATION  
PGA  
CONTROL REGISTER  
MUTE DEFAULT  
Muted (bit-15)  
Not-muted (bit-15)  
Muted (15)  
DAC  
Mixer  
18h  
72h  
02h  
Volume  
Table 2 Gain Control Register Location  
MASTER/SLAVE ID SUPPORT  
WM9707 supports operation as either a master or a slave codec. Configuration of the device as  
either a master or as a slave, is selected by tying the CID pin 45 on the package.  
Fundamentally, a device identified as a master (ID = 0) produces BITCLK as an output, whereas a  
slave (any other ID) must be provided with BITCLK as an input. This has the obvious implication that  
if the master device on an AC link is disabled, the slave devices cannot function.  
The AC97 Revision 2.1 specification defines that the CID pin has inverting sense, and are provided  
with internal weak pull ups. Therefore, if no connections are made to the CID pin, then the pin pulls hi  
and an ID = 0 is selected, i.e. master. External connects to ground will select other IDs.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 2.2 January 2001  
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