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WM8983
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 3 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA = +25oC, Slave Mode
PARAMETER
SYMBOL
TMCLKY
CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK=SYSCLK (=256fs)
MCLK input to PLL Note 1
81.38
20
ns
ns
MCLK cycle time
MCLK duty cycle
TMCLKDS
60:40
40:60
Note:
1. PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
AUDIO INTERFACE TIMING – MASTER MODE
Figure 4 Digital Audio Data Timing – Master Mode (see Control Interface)
PP Rev 1.1 August 2005
13
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
