WM8961
Pre-Production
The internal MICBIAS circuitry is shown in Figure 14.
The maximum source current capability for MICBIAS is 2mA. The external biasing resistors therefore
must be large enough to limit the MICBIAS current to 2mA.
Figure 14 Microphone Bias Schematic
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8961 uses stereo 24-bit, 128x over-sampled sigma-delta ADCs. The use of multi-bit feedback
and high over-sampling rates reduce the effects of jitter and high frequency noise. The ADC Full Scale
input level is proportional to AVDD. With a 1.8V supply voltage, the full scale level is 0.5Vrms. Any
voltage greater than full scale may overload the ADC and cause distortion.
The ADCs are enabled by the ADCL/R register bit. Note that when disabling the ADC, the digital
volume control LADCVOL/RADCVOL[7:0] (R21 (15h)) should be muted (set to 00h), before clearing
ADCL or ADCR to 0. This ensures that the last ADC code does not appear at the Audio Interface
(ADCDAT) pin when ADCL/R are cleared.
REGISTER
ADDRESS
BIT
LABEL
ADCL
DEFAULT
DESCRIPTION
R25 (19h)
Power
3
0
Enable ADC left channel:
0 = ADC disabled
management (1)
1 = ADC enabled
2
ADCR
0
Enable ADC right channel:
0 = ADC disabled
1 = ADC enabled
Table 9 ADC Enable Control
ADCDIV determines the ADC operating clock. The output of ADCDIV should be configured to output a
clock of 256fs. The 256fs output of ADCDIV is further divided such that the ADC operates at 128fs.
PP, August 2009, Rev 3.1
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
