Pre-Production
WM8959
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
9
MICDET_POL
(rw)
0b
MICBIAS current detect polarity
0 = Non-inverted
1 = Inverted
R22 (16h)
10
9
MICSHRT_IRQ_ENA
MICDET_IRQ_ENA
0b
0b
MICBIAS short circuit detect IRQ Enable
0 = disabled
1 = enabled
MICBIAS current detect IRQ Enable
0 = disabled
1 = enabled
Table 41 MICBIAS Current Detect Control
The current detect function operates according to the following the truth table:
LABEL
VALUE
DESCRIPTION
Mic Short Circuit Detect
Mic Short Circuit Detect
Mic Current Detect
Mic Current Detect
0
1
0
1
MCDSCTH current threshold not exceeded
MCDSCTH current threshold exceeded
MCDTHR current threshold not exceeded
MCDTHR current threshold exceeded
Table 42 Truth Table for GPIO Output of MICBIAS Current Detect Function
CLOCK OUTPUT
A clock output (OPCLK) derived from SYSCLK may be output via GPIO1 and GPIO3 to GPIO5.
SYSCLK is derived from MCLK (either directly, or in conjunction with the PLL), and is used to provide
all internal clocking for the WM8959 (see "Clocking and Sample Rates" section for more information).
A programmable clock divider OPCLKDIV controls the frequency of the OPCLK output. This clock is
enabled by register bit OPCLK_ENA. See “Clocking and Sample Rates” for a definition of this
register field.
To enable clock output via one or more GPIO pins, the following register settings are required:
•
•
•
•
•
•
GPIO1_ENA = 1 (only required if using GPIO1)
AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5)
AIF_TRIS = 0
GPIOn_SEL = 0001 for the selected GPIO clock output pin
GPIOn_PU = 0 for the selected GPIO clock output pin
GPIOn_PD = 0 for the selected GPIO clock output pin
PP, May 2008, Rev 3.1
79
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
