Pre-Production
WM8959
REGISTER
ADDRESS
BIT
LABEL
MBSEL
DEFAULT
DESCRIPTION
Microphone Bias Voltage Control
0
0b
0 = 0.9 * AVDD
1 = 0.65 * AVDD
R59 (3Bh)
R60 (3Ch)
PLL (1)
15:0
15:8
7
0000h
00h
Reserved - Do Not Change
Reserved - Do Not Change
Enable PLL Integer Mode
0 = Integer mode
SDM
0b
1 = Fractional mode
6
PRESCALE
0b
Divide MCLK by 2 at PLL input
0 = Divide by 1
1 = Divide by 2
5:4
3:0
00b
8h
Reserved - Do Not Change
Integer (N) part of PLL frequency ratio.
Use values greater than 5 and less than 13.
Reserved - Do Not Change
PLLN
[3:0]
R61 (3Dh)
PLL (2)
15:8
7:0
00h
31h
PLLK
[15:8]
Fractional (K) part of PLL frequency ratio
(Most significant bits)
R62 (3Eh)
PLL (3)
15:8
7:0
00h
26h
Reserved - Do Not Change
PLLK
[7:0]
Fractional (K) part of PLL frequency ratio
(Least significant bits)
R63 (3Fh) to
R127 (7Fh)
Reserved
PP, May 2008, Rev 3.1
147
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
