Pre-Production
WM8959
REGISTER
ADDRESS
BIT
14
LABEL
DEFAULT
DESCRIPTION
Clocking (2)
SYSCLK_SRC
0b
SYSCLK Source Select
0 = MCLK
1 = PLL output
13
CLK_FORCE
0b
Forces Clock Source Selection
0 = Existing SYSCLK source (MCLK or PLL output) must be
active when changing to a new clock source.
1 = Allows existing MCLK source to be disabled before
changing to a new clock source.
12:11
MCLK_DIV
[1:0]
00b
SYSCLK Pre-divider. Clock source (MCLK or PLL output) will
be divided by this value to generate SYSCLK.
00 = Divide SYSCLK by 1
01 = Reserved
10 = Divide SYSCLK by 2
11 = Reserved
10
MCLK_INV
0b
MCLK Invert
0 = Master clock not inverted
1 = Master clock inverted
Reserved - Do Not Change
DAC Sample Rate Divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2.0
011 = SYSCLK / 3.0
100 = SYSCLK / 4.0
101 = SYSCLK / 5.5
110 = SYSCLK / 6.0
111= Reserved
9:5
4:2
00000b
000b
DAC_CLKDIV
[2:0]
1:0
15
00b
0b
Reserved - Do Not Change
Audio Interface 1 Master Mode Select
0 = Slave mode
R08 (08h)
AIF_MSTR1
AIF_MSTR2
AIF_SEL
Audio
Interface (3)
1 = Master mode
14
13
0b
0b
Audio Interface 2 Master Mode Select
0 = Slave mode
1 = Master mode
Audio Interface Select
0 = Audio interface 1
1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2,
GPIO5/DACDAT2)
12:0
15
0040h
0b
Reserved - Do Not Change
R09 (09h)
GPIO1_ENA
AIF_TRIS
GPIO1 Enable
Audio
Interface (4)
0 = GPIO1 not enabled
1 = GPIO1 enabled
14
13
0b
0b
Reserved - Do Not Change
Audio Interface and GPIO Tristate
0 = Audio interface and GPIO pins operate normally
1 = Tristate all audio interface and GPIO pins
Reserved - Do Not Change
12
11
0b
0b
DACLRC_DIR
DACLRC Direction
(Forces DACLRC clock to be output in slave mode)
0 = DACLRC normal operation
1 = DACLRC clock output enabled
PP, May 2008, Rev 3.1
131
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
