Pre-Production
WM8959
REGISTER
ADDRESS
BIT
3:2
LABEL
DEFAULT
DESCRIPTION
Reserved - Do Not Change
00b
0b
1
DACL_ENA
Left DAC Enable
(rw)
0 = disabled
1 = enabled
0
DACR_ENA
(rw)
0b
Right DAC Enable
0 = disabled
1 = enabled
R04 (04h)
15:9
8
0100000b
0b
Reserved - Do Not Change
BCLK Invert
Audio
Interface (1)
AIF_BCLK_INV
AIF_LRCLK_INV
0 = BCLK not inverted
1 = BCLK inverted
7
0b
Right, left and I2S modes – DACLRC polarity
0 = normal DACLRC polarity
1 = invert DACLRC polarity
DSP Mode – mode A/B select
0 = MSB is available on 2nd BCLK rising edge after DACLRC
rising edge (mode A)
1 = MSB is available on 1st BCLK rising edge after DACLRC
rising edge (mode B)
6:5
4:3
AIF_WL
[1:0]
10b
10b
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
AIF_FMT
[1:0]
Digital Audio Interface Format
00 = Right justified
01 = Left justified
10 = I2S Format
11 = DSP Mode
2:0
15
000b
0b
Reserved - Do Not Change
Left DAC Data Source Select
0 = Left DAC outputs left channel data
1 = Left DAC outputs right channel data
Right DAC Data Source Select
0 = Right DAC outputs left channel data
1 = Right DAC outputs right channel data
DAC TDM Enable
R05 (05h)
DACL_SRC
DACR_SRC
AIFDAC_TDM
Audio
Interface (2)
14
1b
13
0b
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
DACDAT TDM Channel Select
0 = DACDAT data input on slot 0
1 = DACDAT data input on slot 1
DAC Input Volume Boost
00 = 0dB
12
AIFDAC_TDM_
CHAN
0b
11:10
DAC_BOOST
[1:0]
00b
01 = +6dB (Input data must not exceed -6dBFS)
10 = +12dB (Input data must not exceed -12dBFS)
11 = +18dB (Input data must not exceed -18dBFS)
Reserved - Do Not Change
DAC Companding Enable
0 = disabled
9:5
4
00000b
0b
DAC_COMP
1 = enabled
3
DAC_COMPMODE
0b
DAC Companding Type
0 = µ-law
1 = A-law
PP, May 2008, Rev 3.1
129
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
