Production Data
WM8955BL
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
DACLRC propagation delay from BCLK falling
edge
tDL
10
ns
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDST
tDHT
10
10
ns
ns
AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
BCLK
DACLRC
DACDAT
tBCY
tLRSU
tDS
tLRH
Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
50
20
20
10
10
10
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC setup time to BCLK rising edge
DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
CONTROL INTERFACE TIMING – 3-WIRE MODE
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
PD Rev 4.1 February 2007
13
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
