WM8955BL
Production Data
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
CLKDIV2 = 0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
TMCLKL
TMCLKH
TMCLKY
TMCLKDS
21
21
ns
ns
ns
54
60:40
40:60
Test Conditions
CLKDIV2 = 1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKL
TMCLKH
TMCLKY
10
10
27
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
tDL
DACLRC
(Output)
tDST
tDHT
DACDAT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Bit Clock Timing Information
BCLK rise time (10pF load)
BCLK fall time (10pF load)
tBCLKR
tBCLKF
3
3
ns
ns
BCLK duty cycle (normal mode, BCLK =
MCLK/n)
tBCLKDS
50:50
BCLK duty cycle (USB mode, BCLK = MCLK)
tBCLKDS
TMCLKDS
PD Rev 4.1 February 2007
12
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
