Production Data
WM8945
REGISTER
ADDRESS
BIT
LABEL
FMT [1:0]
DEFAULT
DESCRIPTION
Digital Audio Interface Format
00 = Reserved
1:0
10
01 = Left Justified
10 = I2S format
11 = DSP/PCM mode
Left DAC Invert
R21 (15h)
DACL_DATINV
ADCL_DATINV
0
0
0
0
DAC Control 1
0 = Left DAC output not inverted
1 = Left DAC output inverted
Left ADC Invert
R25 (19h)
ADC Control 1
0 = Left ADC output not inverted
1 = Left ADC output inverted
Table 44 Audio Data Format Control
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 22 Left Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 23 I2S Justified Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising
edge of BCLK (selected by LRCLK_INV) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
PD, May 2011, Rev 4.1
67
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
