Production Data
WM8945
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data into the WM8945 and outputting ADC data
from it. It uses four pins:
.
.
.
.
ADCDAT: ADC data output
DACDAT: DAC data input
LRCLK: DAC and ADC data alignment clock
BCLK: Bit clock, for synchronisation
MASTER AND SLAVE MODE OPERATION
The digital audio interface can be configured as a Master or a Slave interface, using the MSTR
register bit. The two modes are illustrated in Figure 20 and Figure 21.
BCLK
LRCLK
WM8945
Processor
ADCDAT
DACDAT
Figure 20 Master Mode
Figure 21 Slave Mode
In Master mode, LRCLK and BCLK are configured as outputs, and the WM8945 controls the timing of
the data transfer on the ADCDAT and DACDAT pins.
In Master mode, the LRCLK frequency is determined automatically according to the sample rate (see
“Clocking and Sample Rates”). The BCLK frequency is set by the BCLK_DIV register. BCLK_DIV
must be set to an appropriate value to ensure that there are sufficient BCLK cycles to transfer the
complete data words from the ADCs and to the DACs.
In Slave mode, LRCLK and BCLK are configured as inputs, and the data timing is controlled by an
external master.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R6 (06h)
BCLK_DIV [2:0]
BCLK Frequency (Master mode)
000 = SYSCLK
3:1
011
Clock Gen
control
001 = SYSCLK / 2
010 = SYSCLK / 4
011 = SYSCLK / 8
100 = SYSCLK / 16
101 = SYSCLK / 32
110 = reserved
111 = reserved
MSTR
Digital Audio Interface Mode select
0 = Slave mode
0
0
1 = Master mode
Table 43 Digital Audio Interface Control
PD, May 2011, Rev 4.1
65
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
