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WM8945 参数 Datasheet PDF下载

WM8945图片预览
型号: WM8945
PDF下载: 下载PDF文件 查看货源
内容描述: 单声道低功耗编解码器与视频缓冲器和触摸屏控制器 [Mono Low-Power CODEC with Video Buffer and Touch Panel Controller]
分类和应用: 解码器编解码器控制器
文件页数/大小: 169 页 / 1604 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8945  
Production Data  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Thermal Interrupt status  
REFER TO  
R16 (10h)  
System  
Interrupts  
15  
TEMP_INT  
0
0 = Thermal interrupt not set  
1 = Thermal interrupt set  
This bit is latched when set; it is cleared when the  
register is Read.  
GPIO4 Interrupt status  
0 = GPIO4 interrupt not set  
1 = GPIO4 interrupt set  
14  
13  
12  
11  
10  
9
GP4_INT  
GP3_INT  
0
0
0
0
0
0
0
0
This bit is latched when set; it is cleared when the  
register is Read.  
GPIO3 Interrupt status  
0 = GPIO3 interrupt not set  
1 = GPIO3 interrupt set  
This bit is latched when set; it is cleared when the  
register is Read.  
GPIO2 Interrupt status  
0 = GPIO2 interrupt not set  
1 = GPIO2 interrupt set  
GP2_INT  
This bit is latched when set; it is cleared when the  
register is Read.  
GPIO1 Interrupt status  
0 = GPIO1 interrupt not set  
1 = GPIO1 interrupt set  
GP1_INT  
This bit is latched when set; it is cleared when the  
register is Read.  
TCHDATA_INT  
TCHPD_INT  
AUXADC_INT  
LDO_UV_INT  
Touch Panel Data Ready Interrupt  
0 = Touch Panel Data Ready interrupt not set  
1 = Touch Panel Data Ready interrupt set  
This bit is latched when set; it is cleared when the  
register is Read.  
Touch Panel pen down Interrupt  
0 = Touch Panel Pen Down interrupt not set  
1 = Touch Panel Pen Down interrupt set  
This bit is latched when set; it is cleared when the  
register is Read.  
AUXADC Data Ready Interrupt  
8
0 = AUXADC Data Ready interrupt not set  
1 = AUXADC Data Ready interrupt set  
This bit is latched when set; it is cleared when the  
register is Read.  
LDO Undervoltage Interrupt  
0
0 = LDO Undervoltage interrupt not set  
1 = LDO Undervoltage interrupt set  
This bit is latched when set; it is cleared when the  
register is Read.  
Register 10h System Interrupts  
PD, May 2011, Rev 4.1  
124  
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