Production Data
WM8912
The sequence of signals associated with a single register write operation is illustrated in Figure 46.
Figure 46 Control Interface Register Write
The sequence of signals associated with a single register read operation is illustrated in Figure 47.
SCLK
SDA
D7
D1
R/W
A7
A1
A0
D6
D0
R/W
B15
B9
B8
B7
B1
B0
Rpt
START
(Write)
device ID
ACK
ACK
(Read) ACK
ACK
STOP
START
data bits B15 – B8
data bits B15 – B8
ACK
register address
device ID
Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses
Figure 47 Control Interface Register Read
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 55.
Note that multiple write and multiple read operations are supported using the auto-increment mode.
This feature enables the host processor to access sequential blocks of the data in the WM8912
register map faster than is possible with single register operations.
TERMINOLOGY
DESCRIPTION
Start Condition
S
Sr
Repeated start
A
Acknowledge (SDA Low)
Not Acknowledge (SDA High)
Stop Condition
¯A¯
P
R/¯W¯
ReadNotWrite
0 = Write
1 = Read
[White field]
[Grey field]
Data flow from bus master to WM8912
Data flow from WM8912 to bus master
Table 55 Control Interface Terminology
Figure 48 Single Register Write to Specified Address
PD, Rev 4.0, September 2010
81
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
