欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM8912GEFL/RV 参数 Datasheet PDF下载

WM8912GEFL/RV图片预览
型号: WM8912GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗DAC与耳机驱动器的便携式音频应用 [Ultra Low Power DAC with Headphone Driver for Portable Audio Applications]
分类和应用: 驱动器便携式
文件页数/大小: 128 页 / 1259 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8912GEFL/RV的Datasheet PDF文件第37页浏览型号WM8912GEFL/RV的Datasheet PDF文件第38页浏览型号WM8912GEFL/RV的Datasheet PDF文件第39页浏览型号WM8912GEFL/RV的Datasheet PDF文件第40页浏览型号WM8912GEFL/RV的Datasheet PDF文件第42页浏览型号WM8912GEFL/RV的Datasheet PDF文件第43页浏览型号WM8912GEFL/RV的Datasheet PDF文件第44页浏览型号WM8912GEFL/RV的Datasheet PDF文件第45页  
Production Data  
WM8912  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
3
LINEOUTR_RMV  
_SHORT  
0
Removes LINEOUTR short  
0 = LINEOUTR short enabled  
1 = LINEOUTR short removed  
For normal operation, this bit should  
be set as the final step of the  
LINEOUTR Enable sequence.  
2
1
LINEOUTR_ENA  
_OUTP  
0
0
Enables LINEOUTR output stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should  
be set to 1 after the DC offset  
cancellation has been scheduled.  
LINEOUTR_ENA  
_DLY  
Enables LINEOUTR intermediate  
stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should  
be set to 1 after the output signal path  
has been configured, and before DC  
offset cancellation is scheduled. This  
bit should be set with at least 20us  
delay after LINEOUTR_ENA.  
0
LINEOUTR_ENA  
0
Enables LINEOUTR input stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should  
be set as the first step of the  
LINEOUTR Enable sequence.  
Table 26 Headphone / Line Output Pop Suppression Control  
OUTPUT VOLUME CONTROL  
Each analogue output can be independently controlled using the registers described in Table 27 (for  
Headphone outputs) and Table 28 (for Line outputs). See also the “Analogue Outputs” section for  
details of these output pins, including recommended external components.  
The volume and mute status of each analogue output can be controlled individually using the register  
bits described in Table 27 and Table 28.  
To prevent “zipper noise” when a volume adjustment is made, a zero-cross function is provided on all  
output paths. When this function is enabled, volume updates will not take place until a zero-crossing  
is detected. In the event of a long period without zero-crossings, a timeout will apply. The timeout  
must be enabled by setting the TOCLK_ENA bit, as defined in “Clocking and Sample Rates”.  
The volume update bits control the loading of the output driver volume data. For example, when  
HPOUT_VU is set to 0, the headphone volume data can be loaded into the respective control  
register, but will not actually change the gain setting. The Left and Right headphone volume settings  
are updated when a 1 is written to HPOUT_VU. This makes it possible to update the gain of a  
Left/Right pair of output paths simultaneously.  
PD, Rev 4.0, September 2010  
41  
w
 复制成功!