WM8912
Production Data
DESCRIPTION
Removes HPR short
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
3
HPR_RMV_SHO
RT
0
0 = HPR short enabled
1 = HPR short removed
For normal operation, this bit should
be set as the final step of the HPR
Enable sequence.
2
1
HPR_ENA_OUTP
HPR_ENA_DLY
0
0
Enables HPR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
Enables HPR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after HPR_ENA.
0
7
6
5
HPR_ENA
0
0
0
0
Enables HPR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the HPR
Enable sequence.
R94 (5Eh)
LINEOUTL_RMV
_SHORT
Removes LINEOUTL short
0 = LINEOUTL short enabled
1 = LINEOUTL short removed
Analogue
Lineout 0
For normal operation, this bit should
be set as the final step of the
LINEOUTL Enable sequence.
LINEOUTL_ENA_
OUTP
Enables LINEOUTL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
LINEOUTL_ENA_
DLY
Enables LINEOUTL intermediate
stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after LINEOUTL_ENA.
4
LINEOUTL_ENA
0
Enables LINEOUTL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the
LINEOUTL Enable sequence.
PD, Rev 4.0, September 2010
40
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
