WM8904
Pre-Production
The digital microphone interface requires that MIC1 (Left Channel) transmits a data bit each time that
DMICCLK is high, and MIC2 (Right Channel) transmits when DMICCLK is low. The WM8904 samples
the digital microphone data in the middle of each DMICCLK clock phase. Each microphone must tri-
state its data output when the other microphone is transmitting.
Figure 28 Digital Microphone Interface Timing
The digital microphone interface control fields are described in Table 8.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R39 (27h)
Enables Digital Microphone mode
0 = Audio DSP input is from ADC
12
DMIC_ENA
0
Digital
Microphone 0
1 = Audio DSP input is from digital
microphone interface
When DMIC_ENA = 0, the Digital
microphone clock (DMICCLK) is held
low.
Selects Digital Microphone Data Input
pin
11
DMIC_SRC
0
0 = IN1L/DMICDAT1
1 = IN1R/DMICDAT2
Table 8 Digital Microphone Interface Control
PP, Rev 3.3, September 2012
48
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
