WM8904
Pre-Production
TDM MODE
In TDM mode, it is important that two ADC devices do not attempt to drive the ADCDAT pin
simultaneously. The timing of the WM8904 ADCDAT tri-stating at the start and end of the data
transmission is described below.
Figure 4 Audio Interface Timing - TDM Mode
Test Conditions
AVDD = CPVDD = 1.8V , DGND=AGND=CPGND= =0V, TA = +25oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless
otherwise stated.
PARAMETER
Audio Data Timing Information
CONDITIONS
MIN
TYP
MAX
UNIT
ADCDAT setup time from BCLK falling edge
ADCDAT release time from BCLK falling edge
DCVDD =2.0V
DBVDD =
3.6V
5
ns
DCVDD =
1.08V DBVDD
= 1.62V
15
5
ns
ns
ns
DCVDD =
2.0V DBVDD
= 3.6V
DCVDD =
1.08V DBVDD
= 1.62V
15
PP, Rev 3.3, September 2012
28
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
