Pre-Production
WM8904
SLAVE MODE
tBCY
BCLK (input)
tBCH
tBCL
LRCLK (input)
tLRH
tLRSU
ADCDAT (output)
DACDAT (input)
tDD
tDS
tDH
Figure 3 Audio Interface Timing – Slave Mode
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA = +25oC, Slave Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Interface Timing - Slave Mode
BCLK cycle time
SYMBOL
MIN
TYP
MAX
UNIT
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
50
20
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
DACDAT set-up time to BCLK rising edge
tDD
20
tDS
20
Note: BCLK period must always be greater than or equal to MCLK period.
PP, Rev 3.3, September 2012
27
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
