WM8850
Pre-Production
The input configuration for the SPDIFIN pin is controlled by two register bits in the vendor-specific Get
S/PDIF In Control Verb.
SET VERB
BIT
BITFIELD
NAME
DEFAULT
DESCRIPTION
7A1h
1
CMOS
Thres
0
Selects the logic threshold levels when in
CMOS Mode:
0 = 30% / 70% thresholds
1 = 20% / 40% thresholds
Selects the SPDIFIN Pin mode:
0 = CMOS Mode
0
Pin Mode
Sel
0
1 = Comparator Mode
See Figure 14 for examples of the external connections required in each of the supported S/PDIF
input modes:
Figure 14 SPDIFIN Example External Connections
The vendor-specific S/PDIF In Status Verb can be used to see the current physical status of the
S/PDIF receiver. This verb indicates whether the S/PDIF Receiver circuitry is locked, and the sample
rate of the incoming S/PDIF stream.
GET VERB
BIT
BITFIELD
NAME
DEFAULT
DESCRIPTION
FA0h
3:1
RATE
7h
Recovered sample rate:
0h = Reserved
1h = Reserved
2h = 96 kHz
3h = 88.2 kHz
4h = 48 kHz
5h = 44.1 kHz
6h = 32 kHz
7h = Sample rate not detected
S/PDIF Rx lock flag:
0 = Unlocked
0
LOCK
0
1 = Locked
Note: The RATE value is measured directly from the incoming S/PDIF stream, using the BCLK on the
HDA link as a reference clock. The reported sample rate in the channel status of the S/PDIF stream
is not used to provide this value, so in a situation where the two differ the RATE value in the will
reflect the actual sample rate of the S/PDIF input signal. This assumes that the speed of the BCLK
on the HDA link is within the acceptable tolerance as defined in the HDA Specification.
PP, April 2011, Rev 3.2
58
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
