Pre-Production
WM8850
S/PDIF RECEIVE
S/PDIF Receive functionality is supported using the SPDIFIN pin; this provides an IEC-60958-3
compatible S/PDIF input through the S/PDIF Rx node.
The S/PDIF receiver accepts all common audio sample frequencies from 32kHz to 96kHz, and an on-
chip fully-asynchronous sample rate coverter (SRC) provides the flexibility to interface any supported
incoming S/PDIF rate to the HDA interface without loss of quality. The S/PDIF receiver supports
readback of all 40-bits of the S/PDIF channel status information, but does not decode the user
channel data.
The WM8850 nodes associated with this function are shown in Figure 13:
Figure 13 S/PDIF Receive Path
This section provides a summary of the S/PDIF In and S/PDIF Rx nodes, and describes the vendor-
specific verb functions associated with each.
S/PDIF IN (NID = 10h)
Table 26 gives a summary of the S/PDIF In node:
NODE SUMMARY INFORMATION
NID
10h
Widget Type
Pin Complex
Supported Get Verbs
Supported Set Verbs
Unsolicited Responses
F00h, F07h, F08h, F09h, F1Ch, F8Eh, FA0h, FA1h
707h, 708h, 71Ch, 71Dh, 71Eh, 71Fh, 78Eh, 7A1h
Presence Detect
Lock Status
Recovered Rate Change
Vendor-Specific Verbs
F8Eh, 78Eh : Unsolicited Response Priority Control Verb
FA0h : Get S/PDIF In Status Verb
FA1h, 7Ah : S/PDIF In Control Verb
Table 26 S/PDIF In Node Summary Information
The S/PDIF In node provides control over the physical connection of the input to the S/PDIF receiver.
The node also provides basic status information from the S/PDIF receiver circuitry, such as lock
status and recovered sample rate.
The S/PDIF input circuitry accepts signal levels as described in IEC-60958-3, as well as CMOS
compatible and low-amplitude CMOS compatible signals. This allows for a wide range of external
connectivity to the WM8850 depending on the application, which may range from direct connection of
electrical signals from a coaxial cable through a matching network or from another CMOS device like
an optical receiver or DSP.
PP, April 2011, Rev 3.2
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