WM8850
Pre-Production
INTERNAL PATH VERB (VENDOR-SPECIFIC)
Verb ID
F73h
Payload [7:0]
00h
Response[31:0]
Get
Bits [31:0] in the table below
00000000h
Set1
773h
Bits [7:0] in the table below
Bit
Bitfield Name
Rsvd
RW
R
Default
0000000h
00h
Description
[31:8]
[7:0]
Reserved
Path Sel
RW
Selects source of S/PDIF TX 1 node:
00h = HDA Link
02h = ADC1
03h = MIC1
15h = MIC2
All other values of Path Sel are reserved.
Note: When the internal path (of ADC1 or MIC1 or MIC2) to S/PDIF TX 1 is active, SRC2 is automatically bypassed and Mult,
Base & Div (in the Stream Format Verb) become read only and are programmed by the WM8850 to match the sourced node
settings.
S/PDIF VERB (VENDOR-SPECIFIC)
Verb ID
F80h
Payload [7:0]
00h
Response[31:0]
Get
Set
Bits [31:0] in the table below
00000000h
780h
Bits [7:0] in the table below
Bit
Bitfield Name
Rsvd
RW
R
Default
Description
[31:9]
[8]
00000000h Reserved
SRC_LOCK
R
0
0
SRC2 Lock Flag:
0 = Unlocked
1 = Locked
[7]
SRC_BASE
SRC_MULT
RW
RW
Used to set the base rate frequency:
0 = 48 kHz
1 = 44.1 kHz
[6:4]
0h
Used to set the base rate multiplication factor:
0h = x1 (48 kHz, 44.1 kHz or less)
1h = x2 (96 kHz, 88.2 kHz, 32 kHz)
2h = Reserved
3h = x4 (192 kHz, 176.4 kHz)
4h-7h = Reserved
[3:1]
[0]
SRC_DIV
RW
RW
0h
Used to set the base rate division factor:
0h = divide by 1 (48 kHz, 44.1 kHz)
1h = Reserved
2h = divide by 3 (32 kHz)
3h-7h= Reserved
LINKED_MODE
0
Linked Mode Control:
0 = Linked Mode disabled. S/PDIF Tx 1 and S/PDIF Rx are not linked
and can operate at independent sample rates. The S/PDIF Tx 1 sample
rate is determined by the Stream Format Verb, or, in the case where
SRC2 is enabled, the sample rate is determined by Base, Mult and Div
above.
1 = Link Mode enabled. S/PDIF Tx 1 is linked to S/PDIF Rx, and
operates at a rate (configured by SRC_MULT and SRC_DIV above) that
is synchronous with the recovered sample rate.
PP, April 2011, Rev 3.2
110
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
