Pre-Production
WM8850
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
Supported Stream Formats Parameter (PID = 0Bh)
Bit
[31:3]
[2]
Bitfield Name
Rsvd
RW
R
Default
Description
00000000h Reserved
AC3
R
0
1
1
S/PDIF Tx 1 does not support Dolby AC3 format
[1]
Float32
PCM
R
S/PDIF Tx 1 supports Float32 formatted data
S/PDIF Tx 1 supports PCM formatted data
[0]
R
Processing Capabilities Parameter (PID = 10h)
Bit
Bitfield Name
Rsvd
RW
R
Default
0000h
00h
Description
[31:16]
[15:8]
[7:1]
[0]
Reserved
NumCoeff
Rsvd
R
This widget does not support loadable coefficients
Reserved
R
00h
Benign
R
0
The “Processing Benign State” is not supported
PROCESSING STATE VERB
Verb ID
F03h
Payload [7:0]
00h
Response[31:0]
Get
Set
Bits [31:0] in the table below
00000000h
703h
Bits [7:0] in the table below
Bit
Bitfield Name
Rsvd
RW
R
Default
000000h
00h
Description
[31:8]
[7:0]
Reserved
Processing State
RW
The processing block for the S/PDIF Tx 1 widget node is SRC2. The
processing state is controlled as follows:
00h = Processing Off: SRC2 bypassed
01h = Processing On: SRC2 used
02h = Processing Off: SRC2 bypassed (benign not supported)
03h-7Fh = Reserved
80h-FFh = Vendor Specific – not used
Notes:
1. When the S/PDIF transmitter is linked to the S/PDIF receiver (i.e. in Linked Mode), SRC2 is automatically enabled by the
CODEC, and the processing state register is read only.
2. When Software Formatted S/PDIF is selected, SRC2 is automatically bypassed, and the processing state register is read only.
3. When the internal path (of ADC1 or MIC1 or MIC2) to S/PDIF Tx 1 is active, SRC2 is automatically bypassed
PP, April 2011, Rev 3.2
w
107
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
