WM8786
Production Data
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
MCLK duty cycle
TMCLKY
25
ns
TMCLKDS
60:40
40:60
AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
DOUT propagation delay from BCLK falling edge
t
DL 0
10
ns
tDDA
0
11
ns
PD Rev 4.2 February 2007
8
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
