WM8783
Production Data
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKY
MCLK
tMCLKL tMCLKH
Figure 2 Master Clock Timing
Test Conditions
AVDD = 3.3V, GND = 0V, TA = +25oC.
PARAMETER
Master Clock Timing
MCLK frequency
SYMBOL
1 / TMCLKY
CONDITIONS
MIN
TYP
MAX
UNIT
fs = 8kHz
fs = 16kHz
fs = 32kHz
2.048
4.096
MHz
8.192
fs = 44.1kHz
fs = 48kHz
fs = 88.2kHz
fs = 96kHz
11.2896
12.288
11.2896
12.288
MCLK duty cycle
60:40
40:60
(= TMCLKH : TMCLKL
)
PD, August 2010, Rev 4.0
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