Production Data
WM8782
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDD
50
20
20
10
10
0
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
10
Table 3 Digital Audio Data Timing - Slave Mode
Note:
LRCLK should be synchronous with MCLK, although the WM8782 interface is tolerant of phase variations or jitter on these
signals.
PD, August 2006, Rev 4.2
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
