WM8777
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DEVICE DESCRIPTION
INTRODUCTION
WM8777 is a complete 8-channel DAC, 2-channel ADC audio codec, with integrated S/PDIF
transceiver, analogue tone controls and bass management including analogue volume controls on
each channel.
The device is implemented as four separate stereo DACs and a stereo ADC with flexible input
multiplexer, in a single package and controlled by a single interface.
The four stereo channels may either be used to implement a 5.1 channel surround system, with
additional stereo channel for a stereo mix down channel, or for a complete 7.1 channel surround
system.
An analogue bypass path option is available, to allow stereo analogue signals from any of the 8
stereo inputs to be sent to the stereo outputs via the main volume controls. This allows a purely
analogue input to analogue output high quality signal path to be implemented if required. This would
allow, for example, the user to play back a 5.1 channel surround movie through 6 of the DACs, whilst
playing back a separate analogue or digital signal into a remote room installation.
The WM8777 has two digital audio interfaces. The primary audio interface has separate inputs for
each stereo DAC, and one data output which can output digital data from the ADC, received S/PDIF
data or data received from the secondary audio interface. Data directed to DAC1 is also directed to
the S/PDIF transmitter. The secondary audio interface has a single data input and a single data
output. The input data can be output over the primary audio interface, or converted into S/PDIF
format and output over the S/PDIF transmitter. Both audio interfaces may be configured to operate in
either master or slave mode and support right justified, left justified and I2S interface formats along
with a highly flexible DSP serial port interface.
The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC,
using external resistors to reduce the amplitude of larger signals to within the normal operating range
of the ADC. The ADC input PGA also allows input signals to be gained up to +24dB and attenuated
down to -21dB. This allows the user maximum flexibility in the use of the ADC.
A selectable stereo record output is also provided on RECL/R. It is intended that the RECL/R outputs
are only used to drive a high impedance buffer.
Each DAC has its own digital volume control. The digital volume control changes can be made in
0.5dB steps. In addition a zero cross detect circuit is provided for each DAC. The digital volume
control detects a transition through the zero point before updating the volume. This minimises audible
clicks and ‘zipper’ noise as the gain values change. In addition to this there is an analogue volume
control on each of the tone outputs, with a zero cross detect circuit. The analogue volume control
changes can be made in 1dB steps. When analogue volume zero-cross detection is enabled the
attenuation values are only updated when the input signal to the gain stage is close to the analogue
ground level.
Additionally, 6 of the DAC outputs incorporate an input selector and mixer allowing an external 6
channel, or 5.1 channel signal, to be either switched into the signal path in place of the DAC signal or
mixed with the DAC signal.
Control of internal functionality of the device is by 3-wire SPI or 2-wire serial control interface
selectable by the state of the GPO/MODE pin on power up. The control interface may be
asynchronous to the audio data interface as control data will be re-synchronised to the audio
processing internally.
CSB, SCLK, and SDIN are 5V tolerant with TTL input thresholds, allowing the WM8777 to be used
with DVDD = 3.3V and be controlled by a controller with 5V output.
Operation using a system clock of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided. In
Slave mode selection between clock rates is automatically controlled. In master mode the master
clock to sample rate ratio is set by control bits PAIFTX_RATE and PAIFRX_RATE. The ADC and
DAC may run at different rates within the constraint of a common master clock. For example with
master clock at 24.576MHz, a DAC sample rate of 96kHz (256fs mode) and an ADC sample rate of
48kHz (512fs mode) can be accommodated. Sample rates (fs) from less than 8ks/s up to 192ks/s
are allowed, provided the appropriate system clock is input.
PP Rev 1.94 November 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
