WM8772EFT – 32 LEAD TQFP
Production Data
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001100
5
ADCBCP
0
ADCBCLK Polarity (DSP Modes):
0: normal BCLK polarity
Interface Control
1: inverted BCLK polarity
MUTE PIN DECODE
The MUTE pin can either be used an output or an input. When used as an input the MUTE pins
action can controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE
to. As an output its meaning is selected by the DZFM control bits. By default selecting the MUTE to
represent if DAC1 has received more than 1024 midrail samples will cause the MUTE to be asserted
a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to
apply a softmute to all DACs.
REGISTER ADDRESS
0001100
BIT
LABEL
DEFAULT
DESCRIPTION
MUTE Pin Decode Disable:
0: MUTE pin decode enable
1: MUTE pin decode disable
6
MPD
0
ADC Control
DAC TO ADC SYNC
If the DAC and ADC use the same MCLK, and they are operating in the same fs mode setting the
SYNC bit will improve performance by synchronising the internal clock between the two blocks.
Setting this at any other time may or may not improve or degrade the performance of the device.
REGISTER ADDRESS
0001100
BIT
LABEL
DEFAULT
DESCRIPTION
SYNC Function:
7
SYNC
0
SYNC Control
0: Disable
1: Enable
PD Rev 4.2 October 2005
66
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
