WM8772EFT – 32 LEAD TQFP
Production Data
MASTER MODE DACLRC FREQUENCY SELECT
In Master mode the WM8772EFT generates DACLRC and DACBCLK. These clocks are derived
from the master clock and the ratio of DACMCLK to DACLRC is set by DACRATE.
REGISTER ADDRESS
0001010
BIT
LABEL
DEFAULT
DESCRIPTION
Master Mode
8:6 DACRATE [2:0]
010
DACMCLK:DACLRC Ratio
Select:
Interface Control
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs
ADC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the ADCFMT[1:0] register bits:
REGISTER ADDRESS
0001011
BIT
LABEL
DEFAULT
DESCRIPTION
Interface Format Select
00: Right justified mode
01: Left justified mode
10: I2S mode
1:0 ADCFMT[1:0]
00
Interface Control
11: DSP mode A or B
The ADCIWL[1:0] bits are used to control the input word length.
REGISTER ADDRESS
0001011
BIT
LABEL
DEFAULT
DESCRIPTION
Input Word Length
00: 16 bit data
3:2 ADCIWL[1:0]
00
Interface Control
01: 20 bit data
10: 24 bit data
11: 32 bit data
Note: 32-bit right justified mode is not supported.
In all modes, the data is signed 2's complement.
ADC MASTER MODE SELECT
Control bit ADCMS selects between audio interface Master and Slave Modes. In Master mode
ADCLRC and ADCBCLK are outputs and are generated by the WM8772EFT. In Slave mode
ADCLRC and ADCBCLK are inputs to WM8772EFT.
REGISTER ADDRESS
0001011
BIT
LABEL
DEFAULT
DESCRIPTION
ADC Audio Interface
4
ADCMS
0
Interface Control
Master/Slave Mode Select:
0: Slave mode
1: Master mode
PD Rev 4.2 October 2005
64
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
